framer16 HDL Worker

Wraps a single-channel IQ sample stream into 16-sample positional frames for simulation testing of the folded demod chain.

Detail

The worker contains two processes clocked on ctl_in.clk plus a combinational output process.

Reset

The synchronous reset condition is:

rst <= '1' when (ctl_in.reset = '1' or props_in.init = '1') else '0';

Asserting the init property provides a software-controlled flush without a full OpenCPI control-plane reset, useful when re-running test cases.

Input take

input_out.take <= input_in.ready and (not busy);

The input is consumed (taken) only when the worker is idle. This ensures the current sample is not consumed until the previous 16-beat frame has been fully emitted downstream.

I/Q swap

When props_in.swap_iq = '1', the input data word is byte-swapped at the 16-bit boundary before latching:

in_iq <= input_in.data(15 downto 0) & input_in.data(31 downto 16)
         when props_in.swap_iq = '1' else input_in.data;

This matches the cr_x16 convention (I/real = data[31:16]).

Sequential state (p_seq)

When busy = '0' and an input beat arrives with the correct opcode, the sample is latched into lat_iq, pos_cnt is reset to zero, and busy is set. While busy = '1', each cycle that downstream asserts ready, pos_cnt is incremented. When pos_cnt reaches N_CH - 1 (15), busy is cleared, completing the frame.

Output drive (p_out)

The combinational output process drives:

• valid and give high whenever busy = '1'.

• data equal to lat_iq when pos_cnt = sel, zero otherwise.

• som high on beat 0, eom high on beat 15.

• opcode fixed to complex_short_timed_sample_sample_op_e.

• eof asserted (from eof_seen) only after busy has cleared.

The sel signal is resize(unsigned(props_in.position), 4), a 4-bit unsigned comparison against pos_cnt.

Latency

One input clock cycle of latency is introduced by the lat_iq register. The first output beat of each frame appears on the clock edge after the input sample is taken.

Worker Properties

• ocpi_buffer_size_output

  • Type: ushort

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: True

    • Volatile: False

    • Read back: False

  • Default value: 0

• ocpi_blocked_output

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_max_latency_output

  • Type: ushort

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• ocpi_latency_output

  • Type: ushort

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_messages_output

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_bytes_output

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

Worker Ports

Inputs:

• input

  • Protocol: complex_short_timed_sample

  • Optional: False

Outputs:

• output

  • Protocol: complex_short_timed_sample

  • Optional: False

Worker Ports

Inputs:

• input:

  • Type: StreamInterface

  • Protocol: complex_short_timed_sample-prot

  • ClockDirection: in

  • Data width: 32

Outputs:

• output:

  • Type: StreamInterface

  • Protocol: complex_short_timed_sample-prot

  • Worker EOF: true

  • Clock: input

  • Data width: 32

Utilisation

Utilization reporting is not currently implemented.