DVB-S2 Encoder (`dvbs2_encoder`)

Encode DVB-S2 Baseband frames into complex IQ samples ready for RF transmission.

Function

dvbs2_encoder accepts pre-formatted DVB-S2 Baseband (BB) frames on its input port and produces pulse-shaped, constellation-mapped complex IQ samples on its output port.

Each input message carries a single BB frame preceded by a two-byte header:

Byte 0: 0xB8  — sync marker
Byte 1: MODCOD — DVB-S2 MODCOD field (constellation, code rate, pilots, frame type)
Bytes 2…N: BB frame data

The encoder performs the full DVB-S2 physical-layer processing chain defined in ETSI EN 302 307:

BCH outer coding
LDPC inner coding
Bit interleaving (for higher-order constellations)
Constellation mapping (QPSK, 8PSK, 16APSK, 32APSK)
Physical-layer framing and pilot insertion

The output samples are 32-bit complex values (16-bit I in the upper half, 16-bit Q in the lower half) suitable for direct connection to a Digital Radio Controller (DRC) TX port or a file sink for offline processing.

Interface

<?xml version="1.0"?>
<!-- This is the spec file (OCS) for: dvbs2_encoder
     Add component spec attributes, like "protocol".
     Add property elements for spec properties.
     Add port elements for i/o ports -->
<ComponentSpec>
	<port name="input" producer="false" protocol="ulong_timed_sample-prot"/>
	<port name="output" producer="true" protocol="complex_short_timed_sample-prot"/>
</ComponentSpec>

Opcode Handling

The input port consumes sample opcodes from the ulong_timed_sample protocol. All other opcodes are passed through transparently.

The output port produces sample opcodes using the complex_short_timed_sample protocol.

Properties

None.

This component has no spec-level properties. All configuration is performed through worker-specific properties (see dvbs2_encoder.hdl).

Ports

Inputs:

input: Baseband frame input. Each message is a BB frame with a two-byte.
- Protocol: ulong_timed_sample-prot
- Optional: False

Outputs:

output: Complex IQ sample output. Each sample is a 32-bit word with the.
- Protocol: complex_short_timed_sample-prot
- Optional: False

Implementations

dvbs2_encoder (HDL)

HDL worker wrapping the Open Research Institute dvb_fpga DVB-S2 encoder core as an OpenCPI component.

Example Application

<?xml version="1.0"?>
<application done="file_write">
  <instance component="ocpi.core.file_read" connect="dvbs2_encoder">
    <property name="filename" value="input.bin"/>
  </instance>
  <instance component="ocpi.haifuraiya.components.dvbs2_encoder" connect="file_write">
    <!-- Skeleton application outline, set properties here. Or change this
         example application to do something more real-world appropriate if
         file-read, then component, then file-write is too artifical to be a
         useful example. -->
  </instance>
  <instance component="ocpi.core.file_write">
    <property name="filename" value="output.bin"/>
  </instance>
</application>

Dependencies

The dependencies to other elements in OpenCPI are:

hdl/primitives/dvb_fpga — VHDL wrapper and Vivado block design for the Open Research Institute DVB-S2 encoder core (https://github.com/OpenResearchInstitute/dvb_fpga).
axi — OpenCPI AXI library, used by the HDL worker to bridge raw property access to the encoder’s AXI-Lite configuration interface.

Standard HDL libraries used:

ieee.std_logic_1164
ieee.numeric_std

Limitations

Limitations of dvbs2_encoder are:

HDL implementation only; no RCC worker is provided.
The underlying dvb_fpga primitive is packaged as a Xilinx Vivado block design (design_1) and therefore targets Xilinx FPGAs only.
MODCOD selection is set per-frame via the input stream header; it cannot be changed mid-frame.

Testing

Tested platforms: None

DVB-S2 Encoder (dvbs2_encoder)