dvbs2_encoder.hdl HDL Worker

HDL worker wrapping the Open Research Institute dvb_fpga DVB-S2 encoder core as an OpenCPI component.

Detail

Worker Properties

• regs

  • Type: ulong

    • Array dimensions: ['4884']

  • Access:

    • Parameter: False

    • Writable: True

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_buffer_size_output

  • Type: ushort

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: True

    • Volatile: False

    • Read back: False

  • Default value: 0

• ocpi_blocked_output

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_max_latency_output

  • Type: ushort

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• ocpi_latency_output

  • Type: ushort

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_messages_output

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_bytes_output

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

Worker Ports

Inputs:

• input

  • Protocol: ulong_timed_sample

  • Optional: False

Outputs:

• output

  • Protocol: complex_short_timed_sample

  • Optional: False

Architecture

The worker is implemented in three layers:

1. dvbs2_encoder.hdl (dvbs2_encoder.vhd) — the OpenCPI HDL worker. Bridges the OpenCPI WSI data ports and WCI control/property bus to the dvb_fpga primitive interface.

2. dvb_fpga primitive (hdl/primitives/dvb_fpga/encoder.vhd) — a thin VHDL wrapper entity that re-exposes the signals of the underlying Vivado block design with clean port names.

3. design_1 — a Xilinx Vivado block design containing the Open Research Institute dvb_fpga IP core (https://github.com/OpenResearchInstitute/dvb_fpga) and supporting Xilinx IP blocks (FIR compiler, etc.). Platform-specific variants exist:

   • zynq_core — targets Zynq-7000 devices (ZC706, PlutoSDR, LibreSDR).

   • zynq_ultra_core — targets Zynq UltraScale+ devices (ZCU102).

Signal flow

OpenCPI WSI input          AXI-Stream slave           dvb_fpga encoder
(ulong_timed_sample)  -->  s_axis_tdata/tvalid/  -->  (ORI dvb_fpga IP)
                           tkeep/tlast/tready              |
                                                           v
OpenCPI WSI output         AXI-Stream master          Complex IQ out
(complex_short_timed  <--  m_axis_tdata/tvalid/  <--
 _sample)                  tready

OpenCPI WCI / raw props    AXI-Lite slave
(regs property)       -->  s_axi_lite_*  -->  dvb_fpga register map

The axi.lite32.raw2axi_lite32 converter translates raw OpenCPI property reads and writes into AXI-Lite transactions, giving software direct access to the encoder’s full register map via the regs array property.

Input framing

The worker expects each input message to contain exactly one BB frame in the format produced by the downlink_aci application:

[0xB8][MODCOD][BB frame bytes...][padding to 8-byte alignment]

s_axis_tlast is driven by the eom (end-of-message) signal from the OpenCPI input port, marking the boundary between BB frames to the encoder core.

Backpressure

The worker asserts input_out.take only when both the encoder’s s_axis_tready and the output port’s ready are asserted, implementing correct AXI-Stream backpressure across the full pipeline.

Properties

Name	Type	Length	Access	Description
regs	ulong	4884	R/W	Raw register bank providing direct AXI-Lite access to the dvb_fpga encoder’s internal register map. Registers are 32-bit, word-addressed. See the ORI dvb_fpga register map documentation for register definitions (constellation mapper coefficients, LDPC configuration, etc.).

Worker XML

<!-- This file defines the dvbs2_encoder.hdl HDL application worker. -->
<HdlWorker
    Language='vhdl'
    Libraries='dvb_fpga axi'
    Version='2'
    Spec='dvbs2_encoder'
    firstrawproperty='regs'>
    <property name='regs' type='ulong' arraylength='4884' writable='1' volatile='1' description='bank of registers to configure dvbs2 encoder'/>
    <!-- Enter any augmentation of spec properties using <specproperty> elements here -->
    <!-- Enter any worker-specific properties using <property> elements here -->
    <StreamInterface Name="input" DataWidth="32"/>
    <StreamInterface Name="output" DataWidth="32" InsertEOM="true"/>
</HdlWorker>

Utilization

Utilization reporting is not currently implemented.