dsd_x16 HDL Worker
16-channel time-shared differential detector and adaptive soft quantizer; converts complex symbol pairs into channel-tagged 3-bit soft decisions with an accompanying 16-bit wide soft value for sync correlation.
Detail
The dsd_x16 RTL architecture (rtl of worker) uses a 3-stage
feed-forward pipeline across three clocked processes:
Stage 0 — differential products (``p_in``). On a sample beat
(in_beat and complex_short_timed_sample_sample_op_e), two 16x16
signed multipliers compute:
qi_prod = Q(n) * I_prev(ce)(Q of current, I of stored previous)iq_prod = I(n) * Q_prev(ce)(I of current, Q of stored previous)
I_prev and Q_prev are immediately updated to the current symbol so
they are ready for the next symbol on the same channel. The channel index
ce is carried forward through a 3-entry ch_p / vld_p pipeline
that advances only on in_beat, providing stall-safe tag propagation.
Stage 1 — imaginary subtraction (``p_in``, same process, second clock).
imag_diff <= qi_prod - iq_prod (33-bit signed, 1-bit growth). This is
the imaginary part of x(n) * conj(x(n-1)).
Stage 2 — negation, magnitude tracking, and quantization (``p_quant``).
Fires when in_beat = '1' and vld_p(2) = '1':
soft_n = -(imag_diff[32:17])— top 16 bits of the 33-bit diff, negated (polarity convention frommsk_demod.vhd). Q-format: this is effectively Q0.15 relative to the input Q1.14 symbols fromted_x16.mag = |soft_n|(absolute value, 16-bit unsigned).IIR update:
mag_acc(ce) <= mag_acc(ce) - (mag_acc(ce) >> 8) + mag. The mean= mag_acc[23:8](16-bit) uses the old accumulator so the shift computation and the update are in the same clock cycle without feedback.Shift selection: scan
meanfrom MSB to find its leading-one positionk;shft = max(0, k - (OUT_W - 2))=max(0, k - 1).shifted = shift_right(soft_n, shft)(signed arithmetic shift).Saturate
shiftedto[-3, +3](signed 3-bit).Push to output FIFO: 36-bit word
ch_p(2)[3:0] & soft_n[15:0] & sat_ext[15:0]wheresat_extis the 3-bit quantized soft sign-extended to 16 bits.
Output word packing (bits of the 32-bit output sample):
Output FIFO and FSM. A 64-entry x 36-bit internal FIFO decouples the
quantizer from the WSI output. The output FSM (states OST_IDLE,
OST_M0–OST_M3, OST_S, OST_EOF) emits one 5-beat tagged
message per symbol: four metadata beats (OST_M0–OST_M3) with the
channel id in word 2 bits [3:0], then one sample beat (OST_S) with
the packed soft word. Backpressure from the downstream port is honoured on
every beat via output_in.ready.
Latency. From an accepted input sample beat to the corresponding FIFO
push: 3 clock cycles (stages 0, 1, and 2 each consume one clock). From
FIFO push to first output beat: variable (depends on output port availability
and FIFO drain state), but bounded because input is stalled when the FIFO
occupancy reaches FIFO_DEPTH - 4 = 60.
Reset. rst is asserted on either ctl_in.reset or a pulse on the
init property. All per-channel state arrays (i_prev, q_prev,
mag_acc, symcnt), the pipeline registers, and the FIFO pointers are
cleared synchronously.
Worker Properties
ocpi_buffer_size_outputType:
ushortAccess:
Parameter:
FalseWritable:
FalseInitial:
TrueVolatile:
FalseRead back:
False
Default value:
0
ocpi_blocked_outputType:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
ocpi_max_latency_outputType:
ushortAccess:
Parameter:
TrueWritable:
FalseInitial:
FalseVolatile:
FalseRead back:
False
Default value:
None
ocpi_latency_outputType:
ushortAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
ocpi_messages_outputType:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
ocpi_bytes_outputType:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
Worker Ports
inputProtocol:
complex_short_timed_sampleOptional:
False
outputProtocol:
complex_short_timed_sampleOptional:
False
Inputs:
Outputs:
Worker Ports
Inputs:
input:Type:
StreamInterfaceProtocol:
complex_short_timed_sample-protClockDirection:
inData width:
32
Outputs:
output:Type:
StreamInterfaceProtocol:
complex_short_timed_sample-protWorker EOF:
trueClock:
inputData width:
32
Utilisation
Utilization reporting is not currently implemented.